Howard Mao

I am a hardware engineer at Google on the Platforms team. I received my Ph.D. in electrical engineering from UC Berkeley, where I worked in the ADEPT Lab and was advised by Prof. Randy Katz. My dissertation research was in novel architectures for warehouse scale computers, specifically in disaggregated memory systems.

As part of my research, I've contributed lots of code to the FireSim project. FireSim is a platform for FPGA-hosted cycle-accurate simulation of warehouse scale computers in the AWS cloud. Using FireSim and EC2 F1 instances, you can spin up a cluster of datacenter nodes with custom hardware (from RTL), link them together in a timing-accurate network, and run real operating systems and software on top of them.

I have also contributed RTL to the Rocket Chip RISC-V SoC Generator and created RISC-V Project Template, which has been used as a starting point for many RISC-V-based chip designs.

You can find some of my code on Github and Bitbucket.

Publications

• Designing New Memory Systems for Next-Generation Data Centers Howard Mao
• FPGA Accelerated INDEL Realignment in the Cloud Lisa Wu, David Bruns-Smith, Frank A. Nothaft, Qijing Huang, Sagar Karandikar, Johnny Le, Andrew Lin, Howard Mao, Brendan Sweeney, Krste Asanović, David A. Patterson, and Anthony D. Joseph
• A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET
  Stevo Bailey, Jaeduk Han, Paul Rigge, Richard Lin, Eric Chang, Howard Mao, Zhongkai Wang, Chick Markley, Adam Izraelevitz, Angie Wang, Nathan Narevsky, Woorham Bae, Steve Shauck, Sergio Montano, Justin Norsworthy, Munir Razzaque, Wen Hau Mat, Akalu Lentiro, Matthew Doerflein, Darin Heckendom, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian Richards, Jonathan Bachrach, Elad Alon, and Borivoje Nikolic
• FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
  Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Katz, Jonathan Bachrach, Krste Asanovic
• A 0.37mm2LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2n3m5kFFT accelerator integrated with a RISC-V core in 16nm FinFET
  Angie Wang, Brian Richards, Palmer Dabbelt, Howard Mao, Stevo Bailey, Jaeduk Han, Eric Chang, James Dunn, Elad Alon, Borivoje Nikolić
• Hardware Acceleration for Memory to Memory Copies
  Howard Mao
• The Rocket Chip Generator
  Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman
• The Hwacha Microarchitecture Manual
  Yunsup Lee, Albert Ou, Colin Schmidt, Sagar Karandikar, Howard Mao and Krste Asanović

Archive